The display of video from a frame buffer, in general, requires the generation of at least one address per displayed pixel at a rate determined, (1) by the update rate of the display, (2) by the display resolution, and (3) by the number of color components per pixel. Because it is beyond the update rate and resolution capabilities of a microprocessor, the generation of addresses for the frame buffer is typically implemented either in custom hardware or in an `off-the-shelf` CRT (Cathode Ray Tube) Controller I.C. (Integrated Circuit).
In video imaging systems, which include a solid state multi-channel sensor and solid state memory (such as disclosed in commonly assigned U.S. Pat. No. 5,140,436, issued Aug. 18, 1992, inventor Blessinger), the sensor(s) used in the imaging system and the solid state memory locations in which the video data is stored are tightly-coupled. This is because the number of simultaneous data paths which need access to the frame buffer (solid state memory) are set both by the number of sensor(s) as well as the number of channels within the sensor(s). To accommodate this, frame buffers are implemented with a variety of techniques, such as (1) routing the sources amongst several frame buffer boards, and (2) routing individual sources to separate bits of a wide-word frame buffer board. In either case, the locations where the video data is eventually stored is usually driven by the sensor(s) in the system.
In the display side of a video capture imaging system, display capabilities are typically limited to a small subset of possible formats, due to the complex nature of the organization of the source images in the frame buffer. Additionally, such display subsystems are typically limited to a narrow subset of imagers, and in many cases only one. However, more versatility is obtained by composing the images via a microprocessor, at the expense of limiting update rates to virtually a still-frame rate. In either case, the end result are display systems which are more `imager-oriented` rather than `display-oriented`. Such display systems thus fail to accommodate many useful display organizations.
The role of the `off-the-shelf` CRT Controller I.C. in the generation of frame buffer addresses in a video system is very well defined. Some observations are as follows:
*The CRT Controller typically will generate a series of addresses for each displayed raster at a rate which is lower than the pixel update rate of the display system. Thus, the display system will typically address multiple pixels for each generated address. This limits the minimum word size for the frame buffer. This also forces physically adjacent pixels on the display to be in the same word of the frame buffer. PA1 *The progression of the generated addresses within a raster is typically set to increment by fixed amounts. This limits the ability to accommodate imager structures which involve multiple channels per raster. Additionally, it limits the display to the most basic of modes, usually magnification and reduction, as well as image displacement. PA1 *The number of logical screens which can be supported within the display are limited by the design of the CRT Controller. PA1 an image memory for storing a plurality of images, wherein each of said images has a plurality of pixels; PA1 a video display having a matrix of pixels; PA1 a programmable address generator for producing a user defined sequence of display frames, each of which includes an ordered set of pixels from said image memory, and which is characterized by an ordered set of addresses, one for each display pixel, and an ordered set of pixel group identifiers, one for each display pixel; PA1 wherein said address generator includes a) a programmable mapping memory for storing a pixel descriptor of each display pixel of a display frame, said pixel descriptor including a pixel group identification field, which identifies a group of pixels of said video display, and an address field which includes address information of said image memory of pixels to be displayed; and b) an address manager, which is linked to said mapping memory and said video display, and which has a set of registers and logic circuitry corresponding to each of said pixel groups of said mapping ram and said display, wherein each said set of registers includes a sum register, a delta register, and a mask register register, the collective function of each said sets of registers and corresponding logic circuitry being to modify the address field of a pixel descriptor from said mapping memory to retrieve an image pixel stored in said image memory for display on said video display; and PA1 a control for controlling said video imaging system to sequentially read out said pixel descriptors from said mapping memory, and to process said address field of each read out pixel descriptor, by the pixel group set of registers and logic circuitry of said address manager, which corresponds to the pixel group identifier of said processed pixel descriptor, a) in a display mode, in which the mask register specifies bits of the address field, which may or may not be contiguous, to be modified, by adding the masked bits of the address field of the pixel descriptor to the respective bits of the sum register, by which process a modified address field is generated, whose unmasked bits are composed of the original and respective bits of the address field, and whose masked bits are generated as a result of the latter process; and b) in a frame advance mode in which the mask register specifies bits of the sum register, which are contiguous or not, to be modified, wherein the masked bits of the sum register are added to the respective bits of the delta register, to generate a modified value, whose unmasked bits are composed of the original address field bits and respective bits of the sum register, and whose masked bits are generated by the latter process.
The CRT Controller is therefore not well suited for the generation of physical frame buffer addresses, but is best utilized in the generation of logical display addresses.
Although the generation of frame buffer addresses by means of custom hardware provides the speed necessary to handle both a high update rate and high display resolution, in addition to accommodating specific imager architectures, it does so at the expense of display flexibility.
The above addresses an inherent lack of flexibility in the spatial organization of the displayed image, but there is also a similar lack of flexibility in the temporal nature of how addresses are generated by existing display systems. The ability to display multiple logical screens within the display which have different temporal characteristics can be used to help in the analysis of recorded events. A logical screen is a preselected pixel region of the display. For example, if the display is 512.times.512 pixels, a logical screen could have a smaller pixel region, e.g., 256.times.256 pixels. Other logical screens could be the same or smaller size.
For instance, one may want to display both a fixed frame in one logical screen simultaneously with another logical screen containing a sequenced playback of images from the frame buffer, allowing the user to subjectively compare the two screens. Another application would be the playback of the same session in two logical screens at the same playback rate, with a temporal offset between the two screens. This can be used to look for any autocorrelative features within the recorded event. Alternatively, by using the previous technique but directing the logical screens at two different imagers, cross-correlative features can also be displayed to advantage.
The following patents disclose various video display addressing techniques which do not provide the capability of multiple format display of multiple format sources.
U.S. Pat. No. 4,967,274, issued Oct. 30, 1990, discloses an image data conversion device having an image data memory for storing and outputting picture element data to a DMA transmission system;
U.S. Pat. No. 4,533,952, issued Aug. 6, 1985, inventor Norman, discloses a video special effects processing system for superimposing a key video picture on a reference video picture;
U.S. Pat. No. 4,675,842, issued Jun. 23, 1987, inventor Szenes, discloses an apparatus for the display and storage of television picture information by using a dynamic random access memory accessible from a computer;
U.S. Pat. No. 4,790,025, issued Dec. 6, 1988, inventor Inoue, discloses a processing method of image data, which divides an image into a plurality of sections and subjecting the thus divided images to an image processing in limited memory space;
U.S. Pat. No. 4,755,810, issued Jul. 5, 1988, inventor Knierim, discloses a frame buffer memory having facilitated rapid scrolling of raster displays in either vertical or horizontal directions;
U.S. Pat. No. 4,951,229, issued Aug. 21, 1990, inventor Di Nicola, discloses a memory device having a plurality of addressable memory locations, each of which can be defined uniquely by an address having an X component and a Y component;
U.S. Pat. No. 4,872,001, issued Oct. 3, 1989, inventor Netter, discloses a split screen imaging system including interactive controls operating on random access memories for designating subdisplay images on a split screen;
U.S. Pat. No. 4,928,253, issued May 22, 1990, inventor Yamauchi, discloses the sequential display of images from an image memory to a display memory under control of a host computer and a reprocessing unit to solve the problem of fast image read in and slow read out.
There is thus a problem in the prior art to provide a hardware display sub-system which is configurable to handle a flexible `display-oriented` description of the desired image, while at the same time being capable of handling the various imagers which may be simultaneously connected to the video system.